1. Field of the Invention
The present invention relates to pipeline processors and in particular to such processors having self-testing means for identifying malfunctioning modules therein.
2. Description of the Prior Art
Advances in integrated circuit technology have led to the practical implementation of increasingly sophisticated pipeline processors comprising large numbers of individual circuit modules. Maintaining the processors in operable condition has become a complex task because of the difficulty of identifying malfunctioning modules.
Prior art self-test means for pipeline processors have been proposed which apply to the input of a processor a series of pre-designed, multibit test vectors designed to cause each of the modules therein to produce a series of predetermined, multibit output data. If the series of multibit output data actually produced by the individual modules in response to the applied test vectors are examined, at test points connected to the outputs of the modules, it can be determined whether any module is malfunctioning. In the case of large processors with many modules, however, it is impractical to provide the great number of test points that would be required to implement the above-described examination of outputs.
One prior art self-test system which has been established for testing such large processors (see Benowitz et al, "An Advanced Fault Isolation System for Digital Logic", IEEE Transactions on Computers, May 1975) provides for the inclusion of self-test circuitry in each module. This overcomes the difficulty of providing many test points on a relatively small integrated circuit, but the self-test circuitry added to each module comprises substantial hardware, including parity encoders, an adder, a storage register and a comparator. Not only does this hardware substantially increase the total cost and size of the processor, but the multistep test procedure performed by the self-test circuitry on each module during the application of each test vector to the pipeline processor prevents processing of the test vectors at the full operating speed of the processor. Testing at such a reduced speed decreases the likelihood of detecting intermittent failures caused by inadequate timing margins. In addition to the above-mentioned drawbacks, no means is provided for automatically identifying malfunctioning modules. Rather, the self-test circuitry in each module merely indicates when the module is producing erroneous outputs. Such erroneous outputs can be caused not only by malfunctioning of the module itself, but also by malfunctioning of a more upstream module in the flow of data through the processor.
In another system, a parity encoder is included in selected modules of a processor to provide the parity of output data produced by the module. Parity is the module-two sum of the one-valued bits in a binary-coded word. In accordance with this definition, parity is one-valued if and only if the number of one-valued bits is odd. Parity codes are used in the above system and in the present system to detect faulty modules by performing one of two different types of testing (hereinafter referred to as true-parity testing and parity scan testing) on individual modules. The type of test performed on an individual module depends on the function of the circuitry included in the module.
True parity testing is performed on those modules whose circuitry passes data therethrough with parity unchanged or if changed, does so in a manner by which the parity is deducible from the input data. Such modules are called "deducible parity modules" (dpm). Examples of dpm modules which pass data without parity change include the functions of data transfer, multiplexing, and memory. Examples of "dpm" modules, which pass parity data with a deducible change, include the functions of one's complementing (deducible when the number of bits of the data is known) and the formation of a modulo-two sum. The parity of output data produced by each of these dpm modules is derived by the parity encoder on the module and is compared with the parity of the module's input data from which the output data originated. The latter parity values are propagated through the modules alone with input data applied to the module. Whenever a parity error occurs in the output data produced by a dpm module, an associated comparator produces an error signal. The single test point on each module is connected to a flip-flop which is one-valued in the absence of an error and which is set to zero whenever an error signal is received from the module. The collector of the test-point flip flop values is sequentially interrogated under minicomputer control to detect any faulty modules. An address vector, locating each faulty module detected during interrogation, is produced by the test circuitry.
Parity scan testing is performed on modules that transform data in a manner by which the output parity is not deducible from the input parity. "Non-deducible parity modules" exclude the deducible parity modules mentioned above but include most other digital functions. Non-deducible parity modules include circuitry such as arithmetic logic units, multipliers, and fast Fourier transformers. The parities of the output data produced by these modules can be determined only if the input data and the module functions are known. Thus, for these modules the parity of the input is not useful. However, the parity value of output data produced by each module's parity encoder is provided at a single test point on the module. These modules are tested by applying a sequence of predefined test vectors to the input of the pipeline processor and monitoring the resulting parity values produced in the test points of the individual modules. The sequence of error-free parity values that should be produced by each module, during application of the sequence of test vectors, is predetermined (analytically or experimentally) and stored in a memory. One module at a time is tested by minicomputer controlled circuitry which first stores the series of parity values actually produced by the module and then successively transmits them to the minicomputer for comparison with the predetermined error-free parity value. If the transmitted and predetermined parity codes for the module are not identical, thus indicating that the module is faulty, the minicomputer produces an address locating the module being tested.